Digital PLLs outperform analog PLLs in jitter, phase noise, power, and die area. They also reduce migration risk and cost. They make integration and production test easy. Yet, they have not been widely available. This will change. Perceptia’s newly introduced pPLL08 second-generation digital PLL IP shows that the highest performance requirements can be met. A first version of the IP is optimized for 5G base station operation. It can be paired with the highest performing ADCs and DACs. Yet, its size and power are modest. The IP is expected to change the way that radio designers approach their project.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
Download the article: Achieving Groundbreaking Performance with a Digital PLL 20190129