| Process/Foundry: | GF 65LPe | UMC 40 |
| Size: | 50.5 x 22.6 µm2 | On request |
| Power: | 10-µA | On request |
| Status: | Silicon | Silicon |
Application Diagram
Description
The pPOR01 (GlobalFoundries 65LPe version) is a 3-pin cell monitoring its supply voltage, and providing a reset (POR) signal on power-up and power-down.
On power-up, the circuit holds the POR pin down until about 35-µs after VDD has exceeded a threshold voltage between 860 and 980-mV.
When VDD falls below the reset threshold (between 820 and 930-mV), POR is asserted (after about 35-µs), holding externally connected blocks in reset. There is a hysteresis of about 40-mV between the release and reset thresholds.
The threshold values have been optimized for each corner to ensure that logic cells will operate correctly and D-flipflops will hold state.
The POR signal is output with a delay of about 35-µs in order to filter out noise on the supply.
Users should connect the output of the circuit to a counter that will delay the release of reset. This will provide further filtering of noise on the supply.
Features
- Power-On Reset macrocell for use in 1.2-V +10% cores
- Three-pin operation
- Standard CMOS output
- Thresholds optimized for the process to allow logic to function correctly
- Very low quiescent current, max 10-µA
- Footprint 50.5 x 22.6-µm2 or embedded in a standard pad cell
Options
N/A
Front-end Deliverables
- Datasheet
- Integration guidelines
- Verilog-A model
- SPICE model
- Functional verification test bench
- Characterization report
- LEF abstract
- Corner simulation report (based on extracted layout)
Implementation Deliverables
- GDS2 layout files
- SPICE netlist for LVS
- DRC verification report
- SI verification report
- Integration guidelines
- Test guidelines
Available Services
- Front-end integration support, up to 4 man-hours (included)
- Implementation support, up to 4 man-hours (included)
- Maintenance 12 months, includes design updates and process updates
- Migration
- Customization