Multicore DSP Migration

The original IC:

  • Image processor IC with 16 custom-digital DSP cores
  • Working MPW prototype existed in ST process
  • Design files existed in many versions, however, only the GDS2 files were trusted
  • No test benches available

The challenge:

  • Migrate the design to TSMC
  • TSMC library cells not compatible with ST
  • Mimic the original floorplan in order not to introduce unexpected errors, and in order to keep fast performance
  • Take the design from a schematics-based design environment to a timing-based design environment
  • Make the design testable

Our approach, in collaboration with Cadence:

  • Using LVS, find the correct version of the original schematics of the processor core
  • Recharacterize all original (standard and custom) cells
  • Design and/or modify cells in the TSMC process to have compatibles for all original cells
  • Characterize all cells of the newly created library, and generate all required views for a timing-based environment
  • Insert scan chains into the processor core, and lay it out to become a super cell compatible with the new environment
  • Resynthesize (Cadence), place and route, with the top level of the array of super cells done manually
  • Timing closure, based on new, customer-developed,  test benches


  • First silicon showed the migrated DSP array to be fully functional
  • The customer now had a design that was manufacturable, testable, and that could be taken forward for developing the next generation product!