Eight-Channel 10-Gbps Transceiver

The Project

  • Transmitter and PLL (both Perceptia), receiver (by customer team) in a standard 40-nm CMOS process
  • Low-power all-digital PLL with ultra-low jitter
  • Novel high-speed ESD techniques for TX output and RX input circuits
  • Low-power 24-Gbps TX driver with high ESD performance
  • Completed tapeout in 5 months
  • First-pass success!

Transmit Performance

  • Area ~0.1-mm2, power < 60-mW
  • Measured ESD performance exceeds 2-kV HBM
  • 800-mV peak-to-peak output at 12-Gbps
  • 360-mV peak-to-peak output at 24-Gbps
  • Supports 4 TAP FIR (16 levels of de-emphasis)
  • Simulated 3-ps of output jitter
  • Jitter measured from silicon 22.3-ps for the uncompensated output + 150-mm PCB trace
  • Jitter 4.6-ps with FIR algorithm applied to same case
  • Meets -12dB return loss

PLL Performance

  • Frequency range from 7 – 12.5-GHz
  • RMS jitter less than 250-fs
  • 4.1-ps peak-to-peak
  • 0.05UI peak-to-peak at 12.5-Gbps
  • Low power (< 15-mW at 10-GHz)
  • Dual loop achieves ultra fast lock (< 1-μs) and ultra-low jitter
  • Programmable filter achieves ultra-low jitter with inexpensive 25-MHz crystal
  • Digital loop rejects coupled noise and modulation from phase detector
  • Embedded noise suppression including on-chip supply regulation

PLL jitter measurements – 250-fs typical, lowest achieved 150-fs
Measurements show spectrum delivering 150-fs RMS jitter.
Jitter remains constant across PLL lock range.