The Project
- Demodulator IC for South-American digital TV standard ISDBT
- Partners developed architecture and RTL
- Includes several mixed-signal IPs
- Competitive die size
- 1.5 Million equivalent logic gates
- 12-Mbits SRAM
- 1-Mbit coefficient ROM
- Perceptia performed implementation on GlobalFoundries 65nm process
- EquipIC manages supply chain
Perceptia performed
- Synthesis
- DFT insertion (scan chains, MBIST) and optimization
- Physical implementation
- Automatic test pattern generation (ATPG)
- Chip finishing and tape-in to foundry
- Insertion of USB 2.0 PHY and MAC
- Insertion of dual 10-bit 60-MS/s ADC
Through supply-chain partner EquipIC
- Engineering and production test program development
- System-in-package (SiP) development
- Package and test for prototypes
- Production setup