Overview
Perceptia’s DeepSub™ pPLL08F is a family of all digital RF frequency synthesizer PLLs featuring unparallel performance and power. It has industry leading jitter (sub-300fs), phase noise and compact area suitable for RF applications, including 5G and WiFi at frequencies up to 8GHz. It is suitable for use as an LO and/or clocking ADCs/DACs with demanding SNR requirements.
Perceptia’s second generation pPLL08F family is available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of technologies where it is silicon proven and can quickly port it to other technologies or foundries upon request.
Because the PLL is all-digital, it is also the one of smallest LC tank PLL IP’s in the industry. It features Perceptia proprietary and patented technology that enables it to have lower noise and higher stability than a comparable analog PLL, at a fraction of the die size. It is still low power (< 15mW) and compact (< 0.05 sq mm) while meeting the performance demands of critical RF systems. It minimises interference from other circuits on the same die, making it capable of supporting SNDR better than 60dB. The design includes dedicated DSP circuits to minimise the influence of process, voltage, and temperature (PVT) on PLL behaviour.
The pPLL08F is built using Perceptia’s second generation all digital PLL technology. This robust technology delivers identical performance regardless of PVT conditions. It consumes a small fraction of the area of an analog PLL whilst maintaining comparable performance. pPLL08 integrates easily into any SoC design and includes all the views and models required by back end flows. pPLL08F can be used as an integer-N PLL or as a fractional-N PLL. The fractional-N mode provides a high flexibility to choose the best combination of input and output clock frequencies at the system level.
Perceptia further provides integration support and offers customization and migration services. Please send us a message to find out more or discuss how you can use pPLL08 in your project.
Applications
- RF LO
- Clock for RF ADC/DAC
- 5G and LTE radio (3GPP)
- WiFi Radio (802.11ax)
- SerDes
- Optical transceiver
Please send us a message to find out more or discuss how you can use pPLL08F in your project.
Benefits
- Silicon proven
- Fractional Multiplication with frequencies up to 8GHz
- Extremely low jitter (< 300fs RMS)
- Small size (< 0.05 sq mm)
- Low Power (< 15mW)
- Support for many wireless standards including 5G and WiFi
- Easy integration
Availability
pPLL08F is currently available in the following technologies:
Please ask if your preferred technology is not on this list in case the website is not currently up to date. We can port any PLL to any technology on request.
Features
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
- Reference clock from 5MHz to 1GHz
- Second-generation digital PLL architecture, providing integer and 24 bit fractional multiplication
- Primary PLL output running at the main DCO frequency for lowest noise clocking
- Two further PLL outputs via separate postscalers
- Post-scalers programmable from 1 to 2,040
- Lock-detect output
- PLL output duty cycle better than 49 / 51%
- Highly testable using industry standard flows
- ATPG vectors provided
- Specification of functional tests to supplement ATPG testing
Deliverables
- Datasheet
- Detailed Verilog behavioral model
- Timing models
- LEF5.6 abstract for floor planning/chip assembly
- Integration Guide
- DFT Guide
- Integration support
- Characterization report
- GDSII layout macrocell
- CDL netlist for LVS
- DRC, LVS and SI verification reports
- Netlist model with accompanying documentation allowing integration of the module in scan chains