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# Perceptia Devices Australia

Australia

## Sitemaps

- [XML Sitemap](https://perceptia.com/sitemap.xml): Contains all public & indexable URLs for this website.

## Posts

- [News](https://perceptia.com/news/)
- [Perceptia Releases Design Kit for pPLL03 on Samsung Foundry 14LPU Platform](https://perceptia.com/perceptia-releases-design-kit-for-ppll03-on-samsung-foundry-14lpu-platform/) - Sydney, Australia — 24 August, 2026 — Perceptia Devices, a leader in high-performance clocking IP, today announced the availability of the design kit for its pPLL03 phase-locked loop IP on Samsung Foundry’s 14LPU technology node. The pPLL03 is Perceptia’s low jitter, high-performance PLL IP core targeted at demanding SoC applications including AI accelerators, microprocessors, ADC/DAC
- [Perceptia Devices and Dolphin Semiconductor Partner to Deliver Best-in-Class IP Portfolio Covering Power Management, Clocking, High-Quality Audio and In-Situ Monitoring](https://perceptia.com/perceptia-devices-and-dolphin-semiconductor-partner-to-deliver-best-in-class-ip-portfolio-covering-power-management-clocking-high-quality-audio-and-in-situ-monitoring/) - Sydney, Australia and Meylan, France — 20 April, 2026 — Dolphin Semiconductor and Perceptia Devices Australia today announced a strategic collaboration to deliver an expanded, best-in-class semiconductor IP portfolio. The partnership combines Dolphin Semiconductor’s industry leading solutions in Power Management (switching and linear regulators, voltage monitors and low power oscillators), In-Situ Monitoring (timing monitors) and
- [Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology](https://perceptia.com/perceptia-begins-port-of-ppll03-to-samsung-14nm-process-technology/) - Sydney, Australia — 25 November 2025 — Perceptia Devices, a leader in low-jitter clocking IP, today announced the commencement of a port of its proven pPLL03 phase-locked loop (PLL) to Samsung Foundry’s 14LPU process node. This marks another milestone in Perceptia’s ongoing strategy to make its silicon-proven PLL solutions available across a wide range of
- [Perceptia Announces Availability of Cryogenic 10-bit ADC and DAC IP in GF 22FDX](https://perceptia.com/perceptia-announces-availability-of-cryogenic-10-bit-adc-and-dac-ip-in-gf-22fdx/) - Sydney, Australia – 8 December 2025 – Perceptia Devices today announced the availability of its new cryogenic 10-bit analog-to-digital converter (ADC) and 10-bit digital-to-analog converter (DAC) intellectual property (IP) in GlobalFoundries’ 22FDX® process technology. Developed to operate at cryogenic temperatures, Perceptia’s 10-bit ADC and DAC IP blocks are specifically designed for use in emerging applications
- [Perceptia Updates Design Kit for pPLL03 on GlobalFoundries 22FDX Platform](https://perceptia.com/perceptia-updates-design-kit-for-ppll03-on-globalfoundries-22fdx-platform/) - Sydney, Australia — 06 November, 2025 — Perceptia Devices, a leader in high-performance clocking IP, today announced the availability of an updated design kit for its pPLL03 phase-locked loop IP on GlobalFoundries’ 22FDX® (22nm FD-SOI) technology node. The pPLL03 is Perceptia’s low jitter, high-performance PLL IP core targeted at demanding SoC applications including AI accelerators,
- [Perceptia Begins Port of pPLL03 to Samsung 8nm Process Technology](https://perceptia.com/perceptia-begins-port-of-ppll03-to-samsung-8nm-process-technology/) - Sydney, Australia — 11 September 2025 — Perceptia Devices, a leader in low-jitter clocking IP, today announced the commencement of a port of its proven pPLL03 phase-locked loop (PLL) to Samsung Foundry’s 8LPU process node. The pPLL03 is Perceptia’s ultra-low jitter, high-performance PLL IP core targeted at demanding SoC applications including AI accelerators, microprocessors, ADC/DAC
- [Perceptia Introduces pPLL08N: A Family of Compact Narrow-Band RF PLLs which Complement pPLL08W](https://perceptia.com/perceptia-introduces-ppll08n-a-family-of-compact-narrow-band-rf-plls-which-complement-ppll08w/) - Sydney, Australia – 25 Sep 2025 – Perceptia Devices, a leader in low-jitter clocking IP, today announced the launch of its latest product, pPLL08N, a family of narrow-band RF phase-locked loops (PLLs) designed to complement the company’s widely adopted pPLL08W wide-band solution. The new pPLL08N family delivers all the proven performance and reliability of the
- [Perceptia’s pPLL08W Deployed in Production Tapeout of 5G Radio Chip for Smartphones](https://perceptia.com/perceptias-ppll08w-deployed-in-production-tapeout-of-5g-radio-chip-for-smartphones/) - Sydney, Australia – 09 Oct 2025 – Perceptia Devices, a leader in low-jitter clocking IP, today announced that its pPLL08W wide-range phase-locked loop (PLL) IP has been successfully used in the production tapeout of a 5G radio chip for smartphones. This milestone highlights the robustness, performance, and proven production readiness of Perceptia’s PLL technology in
- [Preliminary Characterisation Report for Perceptia’s pPLL08W in GF 22FDX Now Available](https://perceptia.com/preliminary-characterisation-report-for-perceptias-ppll08w-in-gf-22fdx-now-available/) - Sydney, Australia – 23 Oct 2025 – Perceptia Devices today announced the availability of the preliminary characterisation report for its pPLL08W wide-range phase-locked loop (PLL) IP implemented in GlobalFoundries’ 22FDX® process technology. The report details early performance results of pPLL08W in 22FDX, showing low phase noise and spurs, wide frequency coverage, and low power consumption.
- [Perceptia Appoints Running Springs Technology as Representative for Taiwan and China](https://perceptia.com/perceptia-appoints-running-springs-technology-as-representative-for-taiwan-and-china/) - Taipei, Taiwan — 28 August 2025 — Perceptia Devices, a leading provider of high-performance clocking IP, today announced that it has signed Running Springs Technology as its authorised sales representative for Taiwan and China. Running Springs Technology brings deep regional expertise and a strong track record in supporting semiconductor and IP customers throughout Taiwan and
- [Perceptia Completes Silicon Characterisation of pPLL03 for GF 22FDX – Report Now Available](https://perceptia.com/perceptia-completes-silicon-characterisation-of-ppll03-for-gf-22fdx-report-now-available/) - Sydney, Australia – 14 August, 2025 – Perceptia Devices is pleased to announce that silicon characterisation of its low-jitter phase-locked loop IP for performance computing applications, the pPLL03, has been successfully completed on GlobalFoundries 22FDX process technology. The full characterisation report is now available to qualified customers. The pPLL03 is a compact, fractional-N PLL IP
- [Perceptia Releases Design Kit for pPLL05 on GlobalFoundries 22FDX Platform](https://perceptia.com/perceptia-releases-design-kit-for-ppll05-on-globalfoundries-22fdx-platform/) - Sydney, Australia — 31 July, 2025 — Perceptia Devices, a leader in high-performance clocking IP, today announced the availability of the design kit for its pPLL05 phase-locked loop IP on GlobalFoundries’ 22FDX® (22nm FD-SOI) technology node. The pPLL05 is a compact, ultra-low power, PLL optimised for integration into SoCs targeting low-power and battery operated applications.
- [Perceptia Devices Release pPLL08W, best-in-class RF PLL IP in GF22FDX](https://perceptia.com/perceptia-devices-release-ppll08w-best-in-class-rf-pll-ip-in-gf22fdx/) - Sydney, Australia, 17 Jul 2025 – Perceptia Devices, a provider of digital PLL IP cores, announced today that it has released its pPLL08W RF PLL IP and design kit in GlobalFoundries 22FDX SOI technology.Perceptia Devices announces the release of the pPLL08W, an advanced phase-locked loop (PLL) IP designed to revolutionize on-chip clock generation for RF
- [Specifying a PLL Part 3: Jitter Budgeting for Synthesis](https://perceptia.com/specifying-a-pll-part-3-jitter-budgeting-for-synthesis/) - Download Here
- [Specifying a PLL Part 2: Jitter Basics](https://perceptia.com/specifying-a-pll-part-2-jitter-basics/) - Download Here
- [Specifying a PLL: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR](https://perceptia.com/specifying-a-pll-calculating-pll-clock-spur-requirements-from-adc-or-dac-sfdr/) - Download Here
- [Perceptia Devices Offers Research License](https://perceptia.com/perceptia-devices-offers-research-license/) - Sydney, Australia, May 12, 2020 – Perceptia Devices, a provider of digital PLL IP cores, announced today that it has strengthened its offering for non-commercial customers by offering a low cost research license across all IP cores. Responding to demand from universities, Perceptia now offers the new research license for all available IP, across its
- [Perceptia Joins GLOBALFOUNDRIES Events in Santa Clara, Munich](https://perceptia.com/perceptia-joins-globalfoundries-events-in-santa-clara-munich/) - Perceptia Devices, Inc. and GLOBALFOUNDRIES have agreed that Perceptia will join GLOBALFOUNDRIES in Santa Clara, California, on September 24, 2019, and in Munich, Germany, on October 11, 2019. GLOBALFOUNDRIES will hold its Technology Conference (GTC) in these locations, and Perceptia will be pleased to present its first three IPs available in the 22FDX process: pPLL02F
- [Achieving Groundbreaking Performance with A Digital PLL](https://perceptia.com/achieving-groundbreaking-performance-with-a-digital-pll/) - Digital PLLs outperform analog PLLs in jitter, phase noise, power, and die area. They also reduce migration risk and cost. They make integration and production test easy. Yet, they have not been widely available. This will change. Perceptia's newly introduced pPLL08 second-generation digital PLL IP shows that the highest performance requirements can be met. A
- [Perceptia Second-Generation Digital PLL IP Enters Mass Production](https://perceptia.com/perceptia-second-generation-digital-pll-ip-enters-mass-production/) - November 29, 2018 Morgan Hill, California—Perceptia Devices, Inc., a developer of innovative PLL and timing technology, today announced that its flagship high-end second-generation digital PLL has entered mass production in UMC's 40LP foundry process. The IP, dubbed pPLL08-5G, targets a performance point not achieved in conventional analog PLL, or even a first-generation digital PLL. At
- [Perceptia Devices Strengthens Europe Sales Network](https://perceptia.com/perceptia-devices-strengthens-europe-sales-network/) - Morgan Hill, CA, October 1, 2018 - Perceptia Devices, Inc., a Silicon Valley provider of PLL and RFID IP cores, announced today that it has strengthened its European sales network with Blu Business Development (a.k.a BluBiz, www.blubiz.de) in central and western Europe, and EquipIC (www.equipic.com) in the Netherlands and western Europe. Both BluBiz and EquipIC
- [Perceptia Devices Appoints Vector and SMC as its Korean Representatives](https://perceptia.com/perceptia-devices-appoints-vector-and-smc-as-its-korean-representatives/) - Scotts Valley, CA, June 29, 2017 – Perceptia Devices, Inc., a Silicon Valley provider of PLL and RFID IP cores, announced today that it has appointed Vector Co., of Dae-Jeon, and SMC Co., of Seoul, as its representatives for Korea. Both Vector and SMC will promote the full lines of IP and Perceptia's IC design
- [Perceptia Joins GlobalFoundries FDXcelerator™ Program to Bring PLL Technology to Portable Devices](https://perceptia.com/perceptia-joins-globalfoundries-fdxcelerator-program-to-bring-pll-technology-to-portable-devices/) - Scotts Valley, California – May 25, 2017 – Perceptia Devices, Inc., a developer of innovative phase-locked loop (PLL) and timing technology, today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, an expanding FD-SOI ecosystem to enable faster, broader deployment of the foundry’s 22FDX® and 12 FDX™ FD-SOI processes that support IoT, mobile, and wireless

## Pages

- [Home](https://perceptia.com/) - Perceptia Devices is an IP provider based in Sydney, Australia with a 15-year track record. Perceptia is focused on precision RF and highly integrated PLLs and timing solutions. Perceptia’s specialisation and innovation in PLLs has allowed it to build a portfolio of proprietary and patented architectures and circuits that bring value to demanding timing applications.
- [pPLL08 Family — All Digital Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc](https://perceptia.com/pll/ppll08-family/) - Overview Perceptia’s DeepSub™ pPLL08F is a family of all digital RF frequency synthesizer PLLs featuring unparallel performance and power. It has industry leading jitter (sub-300fs), phase noise and compact area suitable for RF applications, including 5G and WiFi at frequencies up to 8GHz. It is suitable for use as an LO and/or clocking ADCs/DACs with
- [pPLL02 Family - General Purpose All Digital Fractional-N PLLs](https://perceptia.com/pll/ppll02-family/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Availability pPLL02F is currently
- [Success Stories](https://perceptia.com/success-stories/)
- [Contact](https://perceptia.com/contact/)
- [Products](https://perceptia.com/products/)
- [Eight-Channel 10-Gbps Transceiver](https://perceptia.com/sucess-stories/perceptia-40nm-8-channel-10gbps-transceiver/) - The Project PLL Performance Frequency range from 7 - 12.5-GHz RMS jitter less than 250-fs 4.1-ps peak-to-peak 0.05UI peak-to-peak at 12.5-Gbps Low power (< 15-mW at 10-GHz) Dual loop achieves ultra fast lock (< 1-μs) and ultra-low jitter Programmable filter achieves ultra-low jitter with inexpensive 25-MHz crystal Digital loop rejects coupled noise and modulation from
- [pPLL08W-GF22FDX — All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX](https://perceptia.com/pll/ppll08-family/ppll08-gf22fdx/) - Applications RF LO Clock for RF ADC/DAC 5G and LTE radio (3GPP) WiFi Radio (802.11ax) SerDes Optical transceiver Please send us a message to find out more or discuss how you can use pPLL08W in your project. Benefits Fractional Multiplication with frequencies up to 10.6GHz Extremely low jitter (< 300fs RMS) Small size (< 0.05
- [Partners](https://perceptia.com/about-perceptia/partners/) - Foundries Perceptia partners with GLOBALFOUNDRIES, and is a member of the foundry's FDXcelerator™ Partner Program, an FD-SOI ecosystem to enable faster, broader deployment of the foundry’s 22FDX® and 12 FDX™ FD-SOI processes that support IoT, mobile, and wireless applications. As a member of the Partner Program, Perceptia will provide PLL IP and complementary design solutions
- [Contact us](https://perceptia.com/contact-us/) - Perceptia Locations Perceptia Devices Australia Pty Ltd Corporate HeadquartersPerceptia Australia Design CenterLevel 6, 55 Chandos StSt Leonards NSW 2065, Australia Worldwide phone: +61 400 337 805 Email: sales@perceptia.com Perceptia Sales Representatives Taiwan, ChinaGrand Technology Inc.11F-1, No. 440 Chung Hsiao RoadHsinchu, Taiwan+886-3-562-2675Email link KoreaS&MT Global Inc. EuropeBlu Business DevelopmentTannenfleckstrasse 20b82194 Gröbenzell, Germany+49 (0) 171 2475708Email link
- [pPLL05 Family — Low Power All Digital Fractional-N PLLs](https://perceptia.com/pll/ppll02lv-family/) - Applications IoT Embedded Moderate speed digital systems Please send us a message to find out more or discuss how you can use pPLL05 in your project. Benefits Small size (< 0.01 sq mm) Low Power (< 1.0mW) Easy integration Fractional Multiplication Availability pPLL05F is currently available in the following technologies: Please ask if your preferred
- [pPLL05-GF22FDX — Low Power All Digital Fractional-N PLL in GlobalFoundries 22FDX](https://perceptia.com/pll/ppll02lv-family/ppll02lv-gf22fdx/) - Applications IoT Embedded Moderate speed digital systems Please send us a message to find out more or discuss how you can use pPLL05F in your project. Benefits Small size (< 0.01 sq mm) Low Power (< 1.0mW) Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL05F is a low power, low voltage all digital PLL featuring
- [PLL IP](https://perceptia.com/pll/) - Perceptia’s second generation PLLs are available on technologies from 5nm to 40nm and across multiple foundry partners. We are continually expanding the range of products and technologies where they are silicon proven and can quickly port any PLL to other technologies or foundries upon request. We offer 4 lines of PLLs: RF PLLs Performance Computing
- [Management](https://perceptia.com/about-perceptia/management/) - Julian Jenkins - Chief Executive Officer, Founder Julian Jenkins, co-founder of Perceptia devices, is our CEO. He is also an architect of all of Perceptia's PLL IP where he been among the pioneers in the development of all digital PLLs. Julian has several US and international patents as a result of this work. He has
- [Careers](https://perceptia.com/careers/) - Perceptia's design center is in Sydney Australia. We hire engineers as our business grows. If you are interested in working for us, please send us an email. Current positions Junior Design Engineer (Mixed-signal and Analogue IC design) Working in a small Silicon IP design house within a team of 12 engineers. Design of full custom
- [Cookie Policy (EU)](https://perceptia.com/cookie-policy-eu/)
- [pPLL05-GF12LPP — Low Power All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP](https://perceptia.com/pll/ppll02lv-family/ppll02lv-gf12lpp/) - Applications IoT Embedded Moderate speed digital systems Please send us a message to find out more or discuss how you can use pPLL05 in your project. Benefits Small size (< 0.008 sq mm) Low Power (< 0.6 mW) Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL
- [pPLL05-TN7 — Low Power All Digital Fractional-N PLL in TSMC N6/N7](https://perceptia.com/pll/ppll02lv-family/ppll02lv-tn7/) - Applications IoT Embedded Moderate speed digital systems Please send us a message to find out more or discuss how you can use pPLL05 in your project. Benefits Small size (< 0.008 sq mm) Low Power (< 0.5 mW) Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL
- [pPLL05-S14LPP — Low Power All Digital Fractional-N PLL in Samsung 14LPP](https://perceptia.com/pll/ppll02lv-family/ppll02lv-s14lpp/) - Applications IoT Embedded Moderate speed digital systems Please send us a message to find out more or discuss how you can use pPLL05 in your project. Benefits Small size (< 0.008 sq mm) Low Power (< 0.6 mW) Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL
- [pPLL05-S8LPP — Low Power All Digital Fractional-N PLL in Samsung 8LPP](https://perceptia.com/pll/ppll02lv-family/ppll02lv-s8lpp/) - Applications IoT Embedded Moderate speed digital systems Please send us a message to find out more or discuss how you can use pPLL05 in your project. Benefits Small size (< 0.005 sq mm) Low Power (< 0.5 mW) Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL
- [RF IC Design](https://perceptia.com/design-services/rf-ic-design/) - The performance of Perceptia’s PLLs depend on our ability to build reliable RF circuits and systems. We also have extensive RF experience from working on larger projects. You can have access to this capability to work on your projects. Perceptia can design a subsystem for a SoC or ASIC or a complete chip as required.
- [High-Speed Mixed-Signal IC Design](https://perceptia.com/design-services/high-speed-mixed-signal-ic-design/) - The performance of Perceptia's PLLs depend on our ability to build reliable mixed signal circuits running at up to 20GHz. You can have access to this capability to work on your projects. Perceptia can design a subsystem for a SoC or ASIC or a complete chip as required. Please contact sales to discuss how we
- [Design Services](https://perceptia.com/design-services/) - Perceptia offers design services focused on our expertise in: Timing (PLLs, DLLs, oscillators, etc) High speed analog and mixed signal RF Here we can apply the same world leading expertise we use to build our PLL IP to your project. Please contact sales to discuss how we can help make your project a success. Customization
- [IP Customization](https://perceptia.com/design-services/ip-customization/) - While our PLL IP covers the majority of use cases, there are sometimes specific use cases with a need for a PLL characteristic that is not already available. Please visit our IP Catalog to see our existing PLL IP. The Perceptia team is happy to customize our IP to meet specific customer needs - you
- [pPLL03F-UMC40LP - All Digital Fractional-N PLL for Performance Computing in UMC 40LP](https://perceptia.com/pll/ppll03-family/ppll03f-umc40lp/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL03F-TN7 - All Digital Fractional-N PLL for Performance Computing in TSMC N6/N7](https://perceptia.com/pll/ppll03-family/ppll03f-tn7/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL03F-GF12LPP - All Digital Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP](https://perceptia.com/pll/ppll03-family/ppll03f-gf12lpp/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL03F-S14LPP - All Digital Fractional-N PLL for Performance Computing in Samsung 14LPP](https://perceptia.com/pll/ppll03-family/ppll03f-s14lpp/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL03F-S8LPP - All Digital Fractional-N PLL for Performance Computing in Samsung 8LPP](https://perceptia.com/pll/ppll03-family/ppll03p-s8lpp/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL03 Family - All Digital Fractional-N PLLs for Performance Computing](https://perceptia.com/pll/ppll03-family/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL03F-GF22FDX - All Digital Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX](https://perceptia.com/pll/ppll03-family/ppll03-gf22fdx/) - Applications Performance Computing Complex SoCs with many clock domains Low-jitter applications Moderate SNR ADC/DAC Please send us a message to find out more or discuss how you can use pPLL03 in your project. Benefits Fractional multiplication with frequency up to 4GHz Low jitter (< 10ps RMS) Small size (< 0.01 sq mm) Low Power (
- [pPLL08-UMC40LP — All Digital Fractional-N RF Frequency Synthesizer PLL in UMC 40LP](https://perceptia.com/pll/ppll08-family/ppll08-umc40lp/) - Applications RF LO Clock for RF ADC/DAC 5G and LTE radio (3GPP) WiFi Radio (802.11ax) SerDes, Optical transceiver Please send us a message to find out more or discuss how you can use pPLL08F in your project. Benefits Fractional Multiplication with frequencies up to 8GHz Extremely low jitter (< 300fs RMS) Small size (< 0.05
- [pPLL08-S8LPP — All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 8LPP](https://perceptia.com/pll/ppll08-family/ppll08-s8lpp/) - Applications RF LO Clock for RF ADC/DAC 5G and LTE radio (3GPP) WiFi Radio (802.11ax) SerDes Optical transceiver Please send us a message to find out more or discuss how you can use pPLL08F in your project. Benefits Fractional Multiplication with frequencies up to 8GHz Extremely low jitter (< 300fs RMS) Small size (< 0.05
- [pPLL08-S14LPP — All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP](https://perceptia.com/pll/ppll08-family/ppll08-s14lpp/) - Applications RF LO Clock for RF ADC/DAC 5G and LTE radio (3GPP) WiFi Radio (802.11ax) SerDes Optical transceiver Please send us a message to find out more or discuss how you can use pPLL08F in your project. Benefits Fractional Multiplication with frequencies up to 8GHz Extremely low jitter (< 300fs RMS) Small size (< 0.05
- [pPLL08-GF12LPP — All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP](https://perceptia.com/pll/ppll08-family/ppll08-gf12lpp/) - Applications RF LO Clock for RF ADC/DAC 5G and LTE radio (3GPP) WiFi Radio (802.11ax) SerDes Optical transceiver Please send us a message to find out more or discuss how you can use pPLL08F in your project. Benefits Fractional Multiplication with frequencies up to 8GHz Extremely low jitter (< 300fs RMS) Small size (< 0.05
- [pPLL08-TN7 — All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7](https://perceptia.com/pll/ppll08-family/ppll08-tn7/) - Applications RF LO Clock for RF ADC/DAC 5G and LTE radio (3GPP) WiFi Radio (802.11ax) SerDes Optical transceiver Please send us a message to find out more or discuss how you can use pPLL08F in your project. Benefits Fractional Multiplication with frequencies up to 8GHz Extremely low jitter (sub 300fs RMS) Small size (< 0.05
- [Technical Team](https://perceptia.com/about-perceptia/technical-team/) - Perceptia's team has been working on all digital PLLs for the last decade and have now designed two generations of ADPLLs. This has allowed the team to acquire a thorough understanding of ADPLL architectures and their application to RF, ADC/DAC clocking and digital clocking. The team has also acquired expertise in the key building blocks
- [About Perceptia](https://perceptia.com/about-perceptia/) - Perceptia Devices is an IP and design services provider, based in Sydney, Australia and Silicon Valley. It is focused on high-speed and ultra-low-power mixed-signal semiconductor designs. Its specialization and innovation in all-digital PLLs, a distinction from its competitors, allows it to steadily build a portfolio of proprietary and patented architectures and circuits that bring value
- [pPLL02F-UMC40LP - General Purpose All Digital Fractional-N PLL in UMC 40LP](https://perceptia.com/pll/ppll02-family/ppll02f-umc40lp/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL02F
- [pPLL02F-TN7 - General Purpose All Digital Fractional-N PLL in TSMC N6/N7](https://perceptia.com/pll/ppll02-family/ppll02f-tn7/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL02F
- [pPLL02F-S14LPP - General Purpose All Digital Fractional-N PLL in Samsung 14LPP](https://perceptia.com/pll/ppll02-family/ppll02f-s14lpp/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL02F
- [pPLL02F-GF12LPP - General Purpose All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP](https://perceptia.com/pll/ppll02-family/ppll02f-gf12lpp/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL02F
- [pPLL02F-GF22FDX - General Purpose All Digital Fractional-N PLL in GlobalFoundries 22FDX](https://perceptia.com/pll/ppll02-family/ppll02f-gf22fdx/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL02F
- [pPLL02F-S08LPP - General Purpose All Digital Fractional-N PLL in Samsung 8LPP](https://perceptia.com/pll/ppll02-family/ppll02f-s08lpp/) - Applications Moderate speed digital systems Microprocessors General-purpose PLL Please send us a message to find out more or discuss how you can use pPLL02 in your project. Benefits Low jitter (< 18ps RMS) Small size (< 0.01 sq mm) Low Power (< 3.5mW) Support for multi-PLL systems Easy integration Fractional Multiplication Overview Perceptia’s DeepSub™ pPLL02F
- [Other IP](https://perceptia.com/pll/other-ip/) - In addition to our PLLs, Perceptia offer the following IP: RFID Gen-2 EPCglobal UHF RFID Analog Frontend Digital Logic Cell Libraries 10-GHz 40-nm 6-GHz 65-nm Ultra-Low-Leakage 180-nm Various Power-on Reset for Digital Logic Bandgap references Regulators
- [pPOR01 — Power-On Reset](https://perceptia.com/pll/other-ip/power-on-reset/) - Process/Foundry: GF 65LPe UMC 40 Size: 50.5 x 22.6 µm2 On request Power: 10-µA On request Status: Silicon Silicon Application Diagram Description The pPOR01 (GlobalFoundries 65LPe version) is a 3-pin cell monitoring its supply voltage, and providing a reset (POR) signal on power-up and power-down. On power-up, the circuit holds the POR pin
- [Linear Regulators](https://perceptia.com/pll/other-ip/linear-regulators/) - Low-dropout linear regulators available in 40-nm, 65-nm and 180-nm.
- [Bandgap References](https://perceptia.com/pll/other-ip/bandgap/) - We have standard bandgap references available in 40-nm, 65-nm and 180-nm. Our Calibrated Bandgap Voltage Reference (UMC 40-nm) provides an accurate and low-noise reference in low-geometry processes. When combined with optional calibration at test it can deliver a voltage accurate to ±1%. This device is targeted to provide the clean reference voltage required to
- [pRFID01-Sil180-960M — Gen 2 EPCglobal UHF RFID Analog Frontend](https://perceptia.com/pll/other-ip/rfid-2/) - Process/Foundry: Silterra 180nm Size: Contact us Power: < 2 microWatts Status: Silicon Block Diagram Description Features EPCGlobal Class-1 Generation-2 standard for passive tags 860MHz – 960 MHz UHF Options Antenna design (license from partner) Baseband design (license from partner) Front-end Deliverables Datasheet Integration guidelines Packaging guidelines Antenna guidelines Verilog model SPICE model Functional verification test
- [Custom PLLs](https://perceptia.com/pll/other-plls/) - While our PLL IP covers the majority of use cases, there are sometimes specific use cases with a need for a PLL characteristic that is not already available. Please visit our IP Catalog to see our existing PLL IP. The Perceptia team is happy to build a custom PLL to meet specific customer needs –
- [RF Successes](https://perceptia.com/sucess-stories/rf-success/) - The RF team's prior successes include volume shipments for: 90nm 3G TX 180nm 2.5G GSM/Edge 180nm Bluetooth 90nm WCDMA TX 90nm LNA
- [ISDBT Digital TV Implementation](https://perceptia.com/sucess-stories/perceptia-65nm-digital-tv-chip/) - The Project Demodulator IC for South-American digital TV standard ISDBT Partners developed architecture and RTL Includes several mixed-signal IPs Competitive die size 1.5 Million equivalent logic gates 12-Mbits SRAM 1-Mbit coefficient ROM Perceptia performed implementation on GlobalFoundries 65nm process EquipIC manages supply chain Perceptia performed Synthesis DFT insertion (scan chains, MBIST) and optimization Physical implementation
- [Quad 3.125-Gbps SerDes](https://perceptia.com/sucess-stories/quad-3-125g-serdes/) - The Project 4 Channel – 3.125-Gbps SerDes OC-48, XAUI Compliant TSMC 250-nm 4 Metal layers 5.2 by 5.4-mm
- [Multicore DSP Migration](https://perceptia.com/sucess-stories/multicore-dsp-migration/) - The original IC: Image processor IC with 16 custom-digital DSP cores Working MPW prototype existed in ST process Design files existed in many versions, however, only the GDS2 files were trusted No test benches available The challenge: Migrate the design to TSMC TSMC library cells not compatible with ST Mimic the original floorplan in order
- [Enhanced-Security Magnetic Card Reader IC](https://perceptia.com/sucess-stories/enhanced-security-magnetic-card-reader/) - The Project Multi-channel magnetic card reader mixed-signal IP block Low power 6-bit ADC Dual variable gain amplifier stages Low input offset Dual variable-threshold comparators PCI DSS v2.0-compliant Full-custom 180-nm TSMC
- [Success Stories](https://perceptia.com/sucess-stories/) - Eight-channel 10-Gbps transceiver Quad 3.125-Gbps SerDes ISDBT Digital TV Implementation Enhanced-Security Magnetic Card Reader IC Multicore DSP Migration RF Successes

## Categories

- [Press Releases](https://perceptia.com/category/pressreleases/) - Press releases from Perceptia
- [White Papers](https://perceptia.com/category/white-papers/) - Perceptia White Papers