pPLL02 — 1.8-GHz Clocking PLL in 180 nm (Silterra, ON Semiconductor)

Process/Foundry: Silterra and ON Semiconductor 180G
Size: 220 * 230 microns
Power: 36-mW
Status: Silicon-proven

Block Diagram

Perceptia’s DeepSub™ 100-MHz to 2-GHz DSP-based PLL features a very low area footprint, using minimum power, while still providing high performance. This hard macro IP provides the clean high-speed reference clock for digital clocking applications. It features fast lock, and low cycle-to-cycle jitter.

The block diagram above shows the architecture of the PLL. A bang-bang PFD (Phase Frequency Detector) provides input to the DSP which includes a fully configurable loop filter. To increase resolution, the loop filter output is passed through an interpolator to the oscillator.

The post-scaler is available as a companion IP (pDIV), three versions of which are available.


  • Low area
  • Low power
  • Fast lock (1µs)
  • Decoupling caps for lower jitter
  • Scan testable (DSP only)
  • Pre-programmed loop filter


  • Voltage regulation for lower jitter
  • Output divider
  • Input prescaler

Front-end Deliverables

  • Datasheet
  • Integration guidelines
  • Verilog model
  • Functional verification test bench
  • Characterization report
  • LEF abstract
  • Corner simulation report (based on extracted layout)

Implementation Deliverables

  • GDS2 layout files
  • SPICE netlist for LVS (encrypted)
  • DRC/LVS verification report
  • Integration guidelines
  • Test guidelines
  • Production test vectors for DSP (ATPG only)

Available Services

  • Front-end integration support (up to 8 man-hours included)
  • Implementation support (up to 8 man-hours included)
  • Maintenance 12 months, includes design updates and process updates
  • Migration
  • Customization