Custom Digital Experience

Custom-digital implementations and migrations

  • Optimization for low power applications
  • Layout compaction for area and cost optimization
  • Optimization for speed
  • Low noise implementations and power supply calming for integration with sensitive analog blocks
  • Custom implementations of: datapath elements (barrel shifters, register files, etc); processor cores; cache memories

High-speed (multi-GHz) logic implementations

  • High speed CMOS logic blocks
  • Differential and Current Mode Logic (CML) to 10-GHz

Complex IO interfaces

  • Multi-ring pad arrays
  • High-speed IO (> 500-Mbps per pin HSTL/SSTL, Gbps per pin custom IOs)

High Speed

  • Custom CMOS logic implementations running at > 400-MHz in standard 250nm process and > 1.5-GHz in standard 130nm process
  • Ultra-high-speed differential logic > 3-GHz in standard 250nm process and reaching 10-GHz in 130nm processes
  • High speed mux and demux implementations
  • Clock and data recovery implementations

Low-Power Solutions

  • Clock gating and power gating
  • Multi-threshold devices
  • Custom 180nm implementation of a 16×16 processor fabric (256 cores) capable of decoding 24-bit video at 33-fps while dissipating less than 125-mW