Custom Digital Implementation
- Custom Digital implementations and migrations
- Optimization for low-power applications
- Layout compaction for area and cost optimization
- Optimization for speed
- Low-noise implementations and power supply calming for integration with sensitive analog blocks
- Custom implementations of:
- datapath elements (barrel shifters, register files, etc.)
- processor cores
- cache memories
- High-speed logic implementations (multi-GHz speeds)
- High-speed CMOS logic blocks
- Differential and current-mode logic (CML) to 10-GHz
- Complex IO interfaces
- Multi-ring pad arrays
- High-speed IO (>500-Mbps/pin HSTL/SSTL, Gbps/pin custom IOs)
- High speed
- Custom CMOS logic implementations running at >400-MHz in standard 250-nm process and >1.5-GHz in standard 130-nm process
- Ultra high-speed differential logic > 3-GHz in standard 250-nm process and reaching 10-GHz in 130-nm processes
- High-speed mux and demux implementations
- Clock and data recovery implementations
- Low-power solutions
- Clock gating and power gating
- Multi-threshold devices
- Custom digital cell design, to operate in a timing-driven design environment
- Low-noise implementations
- Ripple logic instead of synchronous
- Distributed/phased clocking schemes
- Intra-block and inter-block power supply decoupling caps
- Inter-block power supply damping caps
- Substrate noise isolation schemes (guard rings, well isolation, etc.)
- High-complexity IO implementations
- Multi-ring pad arrays for high density IO (>1100 pins total, >500 signal pins)
- High-speed interfaces (GHz I/O’s, <100ps timing windows)
- High-current and high-dI/dt implementations
- Liaison with supply chain
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