pPLL01-U40-11G — 11-GHz Ultra-Low-Jitter PLL

Process: 40-nm
Foundry: UMC
Size: 400 * 500 microns
Power: 20-mW at 10-GHz
Status: Test silicon

Block Diagram

The block diagram above shows the architecture of the PLL. A bang-bang PFD (Phase Frequency Detector) provides input to the DSP which includes a fully configurable loop filter. To increase resolution, the loop filter output is passed through an interpolator to the oscillator.

Description
Perceptia’s DeepSub™ 9 to 11-GHz DSP-based PLL features unparalleled performance and power. This hard macro IP provides the clean high-speed reference clock required to meet the rigorous demands of SerDes and wireless applications. It features fast lock, and ultra-low phase noise and jitter. Graph 1 shows the circuit’s excellent phase noise performance as a function of the offset to the output carrier. Graph 2 shows its jitter as a function of the lock frequency.

 

The design comes in a small footprint and integrates easily with other circuits. The pPLL01-U40-11G is proven in 40-nm CMOS, so you can be confident in the success of your SoC.
Perceptia provides integration support and offers optional customization and migration services.

Features

  • Output frequency from 9 to 11-GHz
  • Ultra-low jitter less than 300-fs rms
  • Low phase noise -116dBc/Hz (loop bandwidth 10-kHz, measured at 1-MHz offset from 10-GHz output carrier)
  • Ultra-fast lock-in time less than 1-μs
  • Input frequency between one 8th and one 512th of the output frequency
  • Configurable loop filter. Default settings meet industry standards. Can be fully customized to optimize performance in the most demanding applications. Loop bandwidth can be from the kHz to MHz range.
  • Low-power and proprietary noise-immunity technology eliminates PLL-to-PLL interference and allows many instances on one die
  • High noise immunity allows easy SoC integration
  • Built-In Self Test (BIST) features:
    • Quick-lock range check at wafer probe
    • Easy jitter characterization at wafer probe
    • Test vectors for DSP logic
  • Power down mode
    • Caching of last state through low-power mode to enable accelerated lock on power up
  • 1.3 to 1.8-V power supply
  • Embedded noise suppression including on-chip supply regulation
    • No external decoupling required
  • Industrial and commercial operating conditions

Options

  • Other ranges available 6.25-8.25-GHz, 7.0-8.6-GHz, and 8.5-10-GHz
  • Fractional-N

Front-end Deliverables

  • Datasheet
  • Integration guidelines
  • Verilog model
  • SPICE model
  • Functional verification test bench
  • Characterization report
  • LEF abstract
  • Corner simulation report

Implementation Deliverables

  • GDS2 layout files
  • SPICE netlist for LVS
  • DRC verification report
  • SI verification report
  • Integration guidelines
  • Test guidelines
  • Production test vectors (ATPG) for DSP

Available Services

  • Front-end integration support, up to 20 man-hours (included)
  • Implementation support, up to 20 man-hours (included)
  • Maintenance 12 months, includes design updates and process updates
  • Migration
  • Customization