pPLL08-U40LP-8G — Second-Generation Digital Fractional-N PLL with Ultra-Low Jitter

Process: 40-nm
Foundry: UMC
Size: 289 * 392 microns
Power: 60-mW
Status: Volume production

Block Diagram
The block diagram shows the PLL architecture. The core PLL combines a phase accumulator and a phase predictor, both clocked by the reference signal. All blocks in the feedback loop, apart from the Digitally-Controlled Oscillator (DCO) contain synchronous RTL-synthesized logic. The DCO contains critical mixed-signal RF circuitry.

Perceptia’s DeepSub™ 8-GHz second-generation digital PLL features unparalleled performance and power. This hard macro IP provides the clean high-speed reference clock required to meet the rigorous demands of SerDes and wireless applications. It features fast lock, and ultra-low phase noise and jitter. Graph 1 shows the circuit’s excellent phase noise performance as a function of the offset to the output carrier. Graph 2 shows its jitter as a function of the lock frequency.


The design comes in a small footprint and integrates easily with other circuits. The pPLL08-U40LP-8G is proven in 40-nm CMOS, so you can be confident in the success of your SoC.
Perceptia provides integration support and offers optional customization and migration services.


  • Fractional-N digital PLL architecture, using an LC-tank oscillator
  • Ultra-low jitter and ultra-low phase noise, suitable for demanding wired, wireless and optical communications applications
  • A prescaler R (divide by 1 to 7) on the reference clock input generates internal reference clock ck_ref, which may be from 10MHz to 170MHz
  • PLL output frequency (at ck_pll_out) can be from 1 to 2047 times the ck_ref frequency, up to the highest oscillator frequency
  • Twenty-four bits fractional resolution
  • Oscillator output frequency up to 8GHz
  • Direct high-speed PLL output from the oscillator and two post-scalers with lower-speed outputs
  • Configurable loop filter can be customized to optimize performance for specific crystals or reference clock sources. Supports loop bandwidths from sub-kHz to MHz. Default settings are optimized for a 61.44MHz crystal.
  • Lock-detect output
  • Output duty cycle better than 48 / 52%
  • Spread-spectrum clock (SSC) generation
  • High noise immunity allows easy SoC integration
  • Highly testable using industry-standard flows
  • Low power consumption
  • Power-down modes cache the last state to enable accelerated lock on power-up
  • Industrial operating conditions (-40 to 85°C) with junction temperature up to 125°C.

Front-end Deliverables

  • Datasheet
  • Integration guidelines
  • Verilog model
  • SPICE model
  • Functional verification test bench
  • Characterization report
  • LEF abstract
  • Corner simulation report

Implementation Deliverables

  • GDS2 layout files
  • SPICE netlist for LVS
  • DRC verification report
  • SI verification report
  • Integration guidelines
  • Test guidelines
  • Production test vectors (ATPG) for DSP

Available Services

  • Front-end integration support, up to 20 man-hours (included)
  • Implementation support, up to 20 man-hours (included)
  • Maintenance 12 months, includes design updates and process updates
  • Migration
  • Customization