Standard-Cell Digital Implementation

  • From FPGA or netlist to working silicon
    • Provide design standards and best practices for your engineers to write RTL that is synthesizable for IC implementation
    • Guide your FPGA design team towards high-quality synthesized RTL
  • Collaborative process between your expert system designers and our expert physical implementation engineers to get to commercially viable silicon that can be reliably produced in high volume
  • Design-for-Test (DFT)—architecture, implementation and optimization
  • Selection of foundry process and third-party IP
  • Regular technical meetings and project management meetings, and a set number of specific design reviews to keep the work coordinated
  • Incoming inspection of third-party technical contributions
  • Extraction of a post-layout netlist to allow the frontend team to perform post-layout functional verification
  • All other relevant verifications: equivalence, timing closure, physical correctness, signal integrity
  • Test pattern generation
  • Interfacing with the manufacturing supply chain