Perceptia provides IP to support its design services, and design services to support its IP. (1 + 1 > 2!)
Where standard cell libraries couldn’t bring us the speed we need, we have developed our own custom logic cell libraries. Our PLLs use DeepSub™ technology, with an optimized architecture of mixed-signal and DSP elements, in order to create some of the most stable and low-noise timing solutions. If you look at our product briefs, you will find the area and power requirements most compelling too!
Of course we have standard analog blocks including references, regulators, power-on resets, etc. We have productized some of our IP, whereas other IP is available to us from designs we have already done, from which we can duplicate, migrate, or derive new optimized blocks.
- pPLL01-U40-11G — 11-GHz Ultra-Low Jitter LC-tank PLL in UMC 40-nm
- pPLL02-G65LPe-6G — 6-GHz Minimum-Area Low-Power Ring-Oscillator Clocking PLL in GlobalFoundries 65LPe
- pPLL02-Sil180G-2G — 1.8-GHz Minimum-Area Low-Power Ring-Oscillator Clocking PLL in Silterra 180G
- pPLL03-GF65LPe-4G — 4-GHz Jitter-Optimized Low-Power Ring-Oscillator PLL in GlobalFoundries 65LPe
- pPLL03-Sil180G-1G — 1-GHz Jitter-Optimized Low-Power Ring-Oscillator PLL in Silterra 180G
pDIV series – Postscalers for PLL:
- pDIV-GF65LPe-32 Programmable Post-Scaler with M1 = 1 and M2 = 1…256
- pDIV-GF65LPe-128 Programmable Post-Scaler with M1 = 1, 2 or 4 and M2 = 1…32
- pDIV-GF65LPe-1024 Programmable Post-Scaler with M1 = 1, 2 or 4 and M2 = 1…256
Digital Logic Cell Libraries