Welcome to Perceptia!

Perceptia Introduces Second-Generation Digital PLL IP

What Is A “Second-Generation Digital” PLL?

Many companies know that digital PLLs have much to offer over analog PLLs. For one thing, they are much easier to migrate from one process node to another. And they offer advantages in performance, power, die area, features, programmability, predictability, reliability, and testability. Designing the digital PLL

High-Speed Mixed-Signal and Ultra-Low-Power IC Design

Perceptia offers top-of-the-line IP and chip design services. Our technology includes the latest in all-digital PLLs, including:

  • Super small PLLs for logic clocking (pPLL02)
  • Super small low-jitter PLLs for video clocking (pPLL03)
  • Ultra-low-jitter PLLs (brand new pPLL08)
  • Jitter attenuator PLLs
  • Networking PLLs
  • Fractional-N and legacy integer-N PLLs
  • Ultra-low-power FLLs and PLLs

We have additional ultra-low-power technology:

  • UHF RFID tag IC for use without battery
  • IoT
  • Pacemaker

IP and Design Services

Perceptia was founded in 2003 in Silicon Valley, and provides PLL IP and IC design services related to the IP. Our customers are semiconductor companies (IDMs, fabless, design houses) and system companies. Our IP is focused on high-speed timing (PLLs), and IoT. Our design services encompass high-speed mixed-signal and analog/RF (full custom), custom digital, and digital physical design.
Headquartered in California, Perceptia has a mixed-signal design team in Sydney, Australia.

The Perceptia Offering

Perceptia has PLL IP that can be migrated, adapted, and customized. The IP is extremely competitive, thanks to Perceptia’s DeepSub™ technology and an extensive portfolio of digital PLL innovations. We further have EPCglobal RFID IP.

Our mixed-signal and RF IC design services are focused on PLL and high-performance radio for advanced process nodes (65, 40, 28-nm, and 22FDX for GlobalFoundries/IBM, UMC, TSMC, Samsung, etc). For analog design we may use a workhorse 180nm process.

DeepSub™ Technology

DeepSub™ is a technology for PLL and SerDes architectures that provides an optimized mix of analog circuits and DSP. It provides many advantages for designs in 90, 65, 40, 32, and 28-nm processes. Perceptia pioneers this technology.

Engagements

We seek long-term relationships with system and semiconductor companies, where we earn their trust and build a position as a valued extension of their design team or teams. Our focus is on companies that need ICs for wired and wireless communications. We provide turnkey design, collaborative design, and design enablement.