NEWS: Second-Generation Digital PLL Technology Achieves Groundbreaking Performance
High-Speed Mixed-Signal and Ultra-Low-Power IC Design
Perceptia offers top-of-the-line IP and chip design services. Our technology includes the latest in all-digital PLLs, including:
- Super small PLLs for logic clocking (pPLL02)
- Super small low-jitter PLLs for video clocking (pPLL03)
- Ultra-low-power FLLs and PLLs
- Ultra-low-jitter PLLs (pPLL01 and -upcoming- pPLL08)
- Jitter attenuator PLLs
- Networking PLLs
- Fractional-N and legacy integer-N PLLs
We have ultra-low-power technology:
- UHF RFID tag IC for use without battery
Design Services and IP
Perceptia was founded in 2003 in Silicon Valley, and provides IC design services and IP. Our customers are semiconductor companies (IDMs, fabless, design houses) and system companies. Our expertise encompasses high-speed mixed-signal and analog/RF (full custom), custom digital, and digital physical design. Our IP is focused on high-speed timing (PLLs), and IoT.
Headquartered in California, Perceptia has a mixed-signal design team in Sydney, Australia.
The Perceptia Offering
Mixed-signal and RF IC design services, with an emphasis on PLL and high-performance radio for advanced process nodes (90, 65, 40, 28-nm, and 22FDX for GlobalFoundries/IBM, UMC, TSMC, Samsung, etc). For analog design we may use 180 or 130-nm. Perceptia has PLL IP that can be migrated, adapted, and customized. The IP is extremely competitive, thanks to Perceptia’s DeepSub™ technology.
DeepSub™ is a technology for PLL and SerDes architectures that provides an optimized mix of analog circuits and DSP. It provides many advantages for designs in 90, 65, 40, 32, and 28-nm processes. Perceptia pioneers this technology.
We seek long-term relationships with system and semiconductor companies, where we earn their trust and build a position as a valued extension of their design team or teams. Our focus is on companies that need ICs for wired and wireless communications. We provide turnkey design, collaborative design, and design enablement.