Perceptia Introduces Second-Generation Digital PLL IP
What Is A “Second-Generation Digital” PLL?
Many companies know that digital PLLs have much to offer over analog PLLs. For one thing, they are much easier to migrate from one process node to another. And they offer advantages in performance, power, die area, features, programmability, predictability, reliability, and testability. Designing the digital PLL… (before migrating it) is not trivial, so for one-off projects, most companies prefer to design an analog PLL. Or, of course, license a digital PLL that already exists&emdash;even if it may need migrating.
Perceptia has made all-digital PLLs for a decade. Now, it introduces a whole new generation of digital PLLs, with a vastly improved architecture. What is different between second and first-generation PLLs?
An “all-digital” PLL, as insiders call it, is a PLL that has at least its loop filter implemented as a digital filter. That means that the oscillator could be either a voltage-controlled oscillator (VCO) steered by a digital-to-analog converter (DAC), or it could be an integrated digitally-controlled oscillator (DCO). There is no need for a charge pump, because the filter doesn’t need an analog input signal. However, everything else may be the same as in an analog PLL. The feedback circuit may be a programmable divider, and the phase comparator may be a phase-frequency detector (PFD). These are both sensitive mixed-signal blocks that can take relatively much power. They directly impact the PLL’s phase noise and jitter. At Perceptia, we now call such PLLs “first-generation digital” PLLs.
“Second-generation digital” PLLs have a different architecture. In their core, only the DCO and a small part of the feedback block are still mixed signal. Everything else is synthesized logic, operating synchronously. The architecture includes a “phase accumulator” to measure the phase of the DCO output clock, and a “phase predictor” to predict what the DCO output clock phase should be. The “phase comparator” is a subtractor that calculates the phase error, i.e., the input data for the digital loop filter. Unlike a first-generation digital PLL, nowhere in the PLL loop is there a signal that is discrete-level, continuous-time. Since all signal processing is done with digital data instead of continuous-time signals, the PLL is as robust as any digital IP.
Among the benefits that can be had (although not all at the same time): long-term jitter of less than a few hundred femtoseconds, low power and ultra-low power, low-voltage operation, 10X area saving, minimal dependence on corner conditions, ATPG testing, loop filter programmability, fast startup, continued operation when the reference clock drops out or is not trusted, and last but not least, very accurate PLL modeling able to predict exactly how an PLL will operate in an application.
High-Speed Mixed-Signal and Ultra-Low-Power IC Design
Perceptia offers top-of-the-line IP and chip design services. Our technology includes the latest in all-digital PLLs, including:
- Super small PLLs for logic clocking (pPLL02)
- Super small low-jitter PLLs for video clocking (pPLL03)
- Ultra-low-jitter PLLs (brand new pPLL08)
- Jitter attenuator PLLs
- Networking PLLs
- Fractional-N and legacy integer-N PLLs
- Ultra-low-power FLLs and PLLs
We have additional ultra-low-power technology:
- UHF RFID tag IC for use without battery
IP and Design Services
Perceptia was founded in 2003 in Silicon Valley, and provides PLL IP and IC design services related to the IP. Our customers are semiconductor companies (IDMs, fabless, design houses) and system companies. Our IP is focused on high-speed timing (PLLs), and IoT. Our design services encompass high-speed mixed-signal and analog/RF (full custom), custom digital, and digital physical design.
Headquartered in California, Perceptia has a mixed-signal design team in Sydney, Australia.
The Perceptia Offering
Perceptia has PLL IP that can be migrated, adapted, and customized. The IP is extremely competitive, thanks to Perceptia’s DeepSub™ technology and an extensive portfolio of digital PLL innovations. We further have EPCglobal RFID IP.
Our mixed-signal and RF IC design services are focused on PLL and high-performance radio for advanced process nodes (65, 40, 28-nm, and 22FDX for GlobalFoundries/IBM, UMC, TSMC, Samsung, etc). For analog design we may use a workhorse 180nm process.
DeepSub™ is a technology for PLL and SerDes architectures that provides an optimized mix of analog circuits and DSP. It provides many advantages for designs in 90, 65, 40, 32, and 28-nm processes. Perceptia pioneers this technology.
We seek long-term relationships with system and semiconductor companies, where we earn their trust and build a position as a valued extension of their design team or teams. Our focus is on companies that need ICs for wired and wireless communications. We provide turnkey design, collaborative design, and design enablement.